Flash memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
One prior art non-volatile memory cell 10 is shown in FIG. 1. The split gate SuperFlash (SF) memory cell 10 comprises a semiconductor substrate 1 of a first conductivity type, such as P type. The substrate 1 has a surface on which there is formed a first region 2 (also known as the source line SL) of a second conductivity type, such as N type. A second region 3 (also known as the drain line) also of a second conductivity type, such as N type, is formed on the surface of the substrate 1. Between the first region 2 and the second region 3 is a channel region 4. A bit line (BL) 9 is connected to the second region 3. A word line (WL) 8 (also referred to as the select gate) is positioned above a first portion of the channel region 4 and is insulated therefrom. The word line 8 has little or no overlap with the second region 3. A floating gate (FG) 5 is over another portion of the channel region 4. The floating gate 5 is insulated therefrom, and is adjacent to the word line 8. The floating gate 5 is also adjacent to the first region 2. A coupling gate (CG) 7 (also known as control gate) is over the floating gate 5 and is insulated therefrom. An erase gate (EG) 6 is over the first region 2 and is adjacent to the floating gate 5 and the coupling gate 7 and is insulated therefrom. The erase gate 6 is also insulated from the first region 2.
One exemplary operation for erase and program of prior art non-volatile memory cell 10 is as follows. The cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate EG 6 with other terminals equal to zero volt. Electrons tunnel from the floating gate FG 5 into the erase gate EG 6 causing the floating gate FG 5 to be positively charged, turning on the cell 10 in a read condition. The resulting cell erased state is known as ‘1’ state. Another embodiment for erase is by a applying a positive voltage Vegp on the erase gate EG 6, a negative voltage Vcgn on the coupling gate CG 7, and others terminal equal to zero volts. The negative voltage Vcgn couples negatively the floating gate FG 5, hence less positive voltage Vcgp is required for erasing. Electrons tunnel from the floating gate FG 5 into the erase gate EG 6 causing the floating gate FG 5 to be positively charged, turning on the cell 10 in a read condition (cell state ‘1’). Alternately the wordline WL 8 (Vwle) and the source line SL 2 (Vsle) can be negative to further reduce the positive voltage on the erase gate FG 5 needed for erase. The magnitude of negative voltage Vwle and Vsle in this case is small enough not to forward the p/n junction. The cell 10 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate CG 7, a high voltage on the source line SL 2, a medium voltage on the erase gate EG 6, and a programming current on the bit line BL 9. A portion of electrons flowing across the gap between the word line WL 8 and the floating gate FG 5 acquire enough energy to inject into the floating gate FG 5 causing the floating gate FG 5 to be negatively charged, turning off the cell 10 in read condition. The resulting cell programmed state is known as ‘0’ state.
The cell 10 can be inhibited in programming (if, for instance, another cell in its row is to be programmed but cell 10 is to not be programmed) by applying an inhibit voltage on the bit line BL 9. A split gate flash memory operation and various circuitry are described in U.S. Pat. No. 7,990,773, “Sub Volt Flash Memory System,” by Hieu Van Tran, et al, and U.S. Pat. No. 8,072,815, “Array of Non-Volatile Memory Cells Including Embedded Local and Global Reference Cells and Systems,” by Hieu Van Tran, et al, which are incorporated herein by reference.
FIG. 2 depicts a typical prior art architecture for a two-dimensional prior art flash memory system. Die 12 comprises: memory array 15 and memory array 20 for storing data, the memory array optionally utilizing memory cell 10 as in FIG. 1; pad 35 and pad 80 for enabling electrical communication between the other components of die 12 and, typically, wire bonds (not shown) that in turn connect to pins (not shown) or package bumps that are used to access the integrated circuit from outside of the packaged chip; high voltage circuit 75 used to provide positive and negative voltage supplies for the system; control logic 70 for providing various control functions, such as redundancy and built-in self-testing; analog logic 65; sensing circuits 60 and 61 used to read data from memory array 15 and memory array 20, respectively; row decoder circuit 45 and row decoder circuit 46 used to access the row in memory array 15 and memory array 20, respectively, to be read from or written to; column decoder 55 and column decoder 56 used to access the column in memory array 15 and memory array 20, respectively, to be read from or written to; charge pump circuit 50 and charge pump circuit 51, used to provide increased voltages for program and erase operations for memory array 15 and memory array 20, respectively; high voltage driver circuit 30 shared by memory array 15 and memory array 20 for read and write (erase/program) operations; high voltage driver circuit 25 used by memory array 15 during read and write operations and high voltage driver circuit 26 used by memory array 20 during read and write (erase/program) operations; and bitline inhibit voltage circuit 40 and bitline inhibit voltage circuit 41 used to un-select bitlines that are not intended to be programmed during a write operation for memory array 15 and memory array 20, respectively. These functional blocks are understood by those of ordinary skill in the art, and the block layout shown in FIG. 2 is known in the prior art.
FIG. 3 depicts a prior art sensing circuit 100. Sensing circuit 100 is an example of the type of circuit that can be used as sensing circuits 60 and 61 in FIG. 2. Sensing circuit 100 comprises memory data read block 110, memory reference read block 120, and differential amplifier block 130.
Memory data read block 110 in this example comprises current source 111, cascoding sensing NMOS transistor 113, bitline clamp NMOS transistor 114, and diode connected sensing load PMOS transistor 112.
Memory reference read block 120 in this example comprises current source 121, reference bitline clamp NMOS transistor 124, cascoding sensing NMOS transistor 123, and diode connected sensing load PMOS transistor 122.
Differential amplifier block 130 in this example comprises input differential pair NMOS transistor 131 and 134, current mirror load PMOS transistor 132 and 133, output PMOS transistor 135, current bias NMOS transistor 136, output current bias NMOS transistor 137, and output 140.
Node 116 is coupled to the selected memory cell (not shown) to be read, and node 117 is coupled to the reference memory cell (not shown) to be used to determine the value of the selected memory cell, or alternatively, a non-memory cell reference bias such as from a replica bias such as from a band-gap or other reference circuit with appropriate compensation to the design or process environment errors is used to determine the value of the selected memory cell.
Differential amplifier block 130 is used to compare the signals received from memory data read block 110 and memory reference read block 120 to generate output 140 which indicates the value of the data stored in the selected memory cell. These components are connected to one another as shown in FIG. 3.
During operation, differential amplifier block 130 will compare the current drawn by memory data read block 110 (through the node 116) and memory reference read block 120 (through the node 117) to generate output 140. If the current drawn by memory data read block 110 exceeds the reference current drawn from memory reference read block 120 (signifying that a “1” is stored in the selected memory cell), then output 140 will be high. If the current drawn from memory data read block 110 is less than the current drawn from memory reference read block 120 (signifying that a “0” is stored in the selected memory cell), then output 140 will be low.
Sensing circuit 100 typically requires an operating voltage of 1.8-3.3 volts. As the size of flash memory cells and arrays diminish in size, what is needed is an improvement to sensing circuit 100 that can function with a lower operating voltage (such as <1.1 volts) and lower power consumption. What is further needed is a sensing circuit that can compensate for non-idealities such as transistor mismatch and memory array mismatch.